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TEST Generation Algorithm for Scheduling LOGIC BLOCKS

IP.com Disclosure Number: IPCOM000036705D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29

Publishing Venue

IBM

Related People

Authors:
Shearon, PC [+details]

Abstract

An algorithm for scheduling logic blocks used in the test generator ETG, increased test coverage and reduced running time for generating tests on logic circuits is described. The algorithm describes the test generation process to meet an objective as it relates to the scheduling of blocks so that the test value on the objective block can be propagated to the primary outputs or shift register latches (SRLs) and the logic values required for this propagation can be justified back to the primary inputs or SRLs. The scheduling of blocks is shown in the flow chart in Fig. 1.