Browse Prior Art Database

Integrated Store Immediate Operations

IP.com Disclosure Number: IPCOM000036707D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29

Publishing Venue

IBM

Related People

Authors:
Ngai, CH Otero, D [+details]

Abstract

When an instruction processing unit (IPU) is executing a 370 instruction of integrated store immediate operation (SI-OPS), for example, AND Immediate (AI), OR Immediate (OI), and Exclusive OR Immediate (EOI), where one operand is included in the instruction (i.e., immediate) and the other is obtained from storage (in this case a fast read/ write (RD/WR) buffer or cache), it would originally take three microwords or up to 14 clock pulses to complete the operation. The sequence of events would be as follows: 1. A RD micro-word is issued to obtain the second operand from storage. 2. A one-byte logical micro-word is then issued which includes the first operand to perform the indicated operation. The Op-code will indicate the operation to take place.