Time Delay Circuit for Harper PNP Array Clock Chopper
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29
The circuit is used to delay the closing edge of the write clock for a static memory using a saturating Harper-PNP cell. The delay circuit contains a saturating HPNP cell identical to the cells within the memory. The time required to write a saturating cell is highly variable depending greatly on hard-to-control process parameters, thus requiring a tracking delay to guarantee stable writing of the memory elements.