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IBM System/370 Floating-Point Response Performance Improvement

IP.com Disclosure Number: IPCOM000036717D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29

Publishing Venue

IBM

Related People

Authors:
Hrusecky, DA [+details]

Abstract

Having a very powerful floating-point (FP) unit operating as a coprocessor to a host processor is quite common in computer design today. A FP coprocessor with the ability to concurrently execute FP instructions for a host processor that must maintain precise interrupts, must have a means for precisely interrupting the host if service is needed. For simple machines, where no interruption stack is implemented, this situation is contradictory until the advent of the 9370 Engineering Scientific Accelerator (ESA). For the ESA, the performance of FP operation sequences is highly dependent upon the speed in which the (Image Omitted) ESA can generate an unlocking signal back to the host S/370 processor. Early Response hardware had been included in the ESA to boost this performance for some add, multiply and divide functions.