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Algorithm to Automatically Determine the Optimum Methodology for Processing Logic Circuits

IP.com Disclosure Number: IPCOM000036719D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29

Publishing Venue

IBM

Related People

Authors:
Shearon, PC [+details]

Abstract

An algorithm, implemented in the test generator ETG, automatically determines the optimum methodology (in terms of test coverage, run time, and test patterns) for processing logic circuits. It does this based on information available from the user, information available about the logic circuit, and the test generation capabilities available in ETG. The three basic types of information it works with are the user and part characteristics (METHCODE), the various modes of test generation capabilities (MODECODE), and the various approaches to test generation on objectives (OBJCODE). Each type of information is described in the following: METHCODE is shown as follows: C5 C4 C3 C2 C1 Where: METHCODE MEANING '10'X C5=1: Multiple input changes required.