Bus ECC for High Availability and Recovery in Real Time
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29
Bus problems are generally the highest solid and intermittent failures in current processor systems, and detection and isolation are a major problem. Recovery for intermittent failures and isolation for solid failures is necessary. By adding error checking and correction (ECC) to a bus address and data lines, you will obtain full recovery for single-bit errors and isolation for multi-bit errors.