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Overlay and Process Bias Monitor Measured by Voltage Contrast Scanning Electron Microscopy

IP.com Disclosure Number: IPCOM000036779D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29

Publishing Venue

IBM

Related People

Authors:
Bentson, LR Sprogis, EJ [+details]

Abstract

Patterns in two levels of materials, at least one of which is a conductor, are measured for overlay and process bias with a special monitor observed by scanning electron beam microscope (SEM) voltage contrast due to beam charging. Measurement of alignment of a conductor pattern to a via hole pattern in an insulating layer over a doped substrate is described to illustrate the method. More detail may be found in the paper "An Overlay Vernier and Process Bias Monitor Measured by Voltage Contrast SEM" by Edmund J. Sprogis, published in the Proceedingsof the 1989 IEEE International Conference on Microelectronic Test Struc- tures, March 15, 1989, Edinburgh, Scotland.