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This article describes a multiple fin polysilicon storage node placed over a transistor switch cell, resulting in a dense and high signal capacity DRAM semiconductor cell configuration.
English (United States)
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Multiple Fin Polysilicon Storage Node Over a Transistor Switch Cell
This article describes a multiple fin polysilicon storage node placed over a
transistor switch cell, resulting in a dense and high signal capacity DRAM
semiconductor cell configuration.
As spacing between devices narrows, moving the storage node either above
or below the transfer device allows the space between transistors to shrink and
still maintain a reasonable storage node area. This memory cell design does not
use the currently popular trench and strapping process to structure a storage
node; rather a multiple fin storage means is utilized.
The following describes the sequence of steps required to make a high
density DRAM cell with a finned capacitive storage node located over the
Define recessed oxide (ROX) regions. Any isolation
may be used.
Implant, grow ROX and tailor.
Grow gate oxides.
Deposit polysilicon or silicides, if used.
Deposit Pyro cap layer. (1,000 - 2,000 angstroms is
Deposit 500 - 1,000 angstroms of nitride.
Define polysilicon gates and interconnects and then
Deposit Pyro and etch to form spacers.
Deposit nitride to increase spacer thickness and etch.
Implant source/drain (S/D) and reoxidize.
Deposit 10,000 angstroms of intrinsic polysilicon.
Deposit 1,500 angstroms of nitride as an etch stop.
Deposit 1,000 angstroms of Pyro as an etch mask.
Define node areas and open nitride and Pyro.
Selective etch down to S/D oxide. Cap protects
Oxidize intrinsic polysilicon fill to form sidewall
Etch bottom to open diffused node region.
Deposit approximately 1,000 angstroms of polysilicon.