Elimination of Bus Contention During Chip-To-Chip Connectivity Test
Original Publication Date: 1989-Nov-01
Included in the Prior Art Database: 2005-Jan-29
Disclosed is a method that eliminates bus contention during chip-to- chip DC connectivity testing for chips with boundary scan latches. The approach imposes a "one talker, many listeners" protocol by selectively disabling the primary outputs of the driving chips over a serial nonfunctional bus. First, the configuration of a chip with boundary scan latches and a model for the chip-to-chip wiring on a card are given, then the proposed solution preventing bus contention is explained.