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Enhanced Rotator Design for Aligning Store Data Disclosure Number: IPCOM000036857D
Original Publication Date: 1989-Nov-01
Included in the Prior Art Database: 2005-Jan-29

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Groves, RD [+details]


RISC processors, like the 801 and ROMP, have a 32-bit rotator as part of their execution unit. These processors must also support store instructions in which the bytes contained in the General-Purpose Register (GPR) being stored need to be rotated to align with the appropriate bytes on the memory/cache interface. This can be further complicated in a processor which supports misaligned operations, string instructions, and byte-reversed stores. By making a relatively minor modification to the rotator design and with an innovative rotator control circuit, the rotator can be shared for all of these functions with very little additional circuitry.