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Algorithmic Pattern Generation at the Tester Disclosure Number: IPCOM000036859D
Original Publication Date: 1989-Nov-01
Included in the Prior Art Database: 2005-Jan-29

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Ellison, JJ Forlenza, DO Hoang, AT Ngo, NN Schafer, JL Wu, SH Swan, RD [+details]


It is proposed to use automated algorithmic pattern generation (APG) to generate test patterns for any memory configuration used in semiconductor devices. The proposal will reduce test data volume and test time for arrays embedded within level-sensitive scan design (LSSD) logic.