Asymmetrical Register File Cell With Isolation From Read Bit Lines
Original Publication Date: 1989-Nov-01
Included in the Prior Art Database: 2005-Jan-29
Fig. 1 shows a circuit schematic of a prior-art memory cell. In this cell, it is possible to destroy the memory cell contents through the read devices 5 and 6, since the cell node "a" is not isolated from the read bit lines (out 0 and 1). Although destructive readout of a "0" is prevented by making device 4 large in comparison to devices 5 and 6, it is, nevertheless, still possible to destroy a "1" in the cell unless the bit lines are restored to a 1 level between consecutive reads of different words.