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Highly Parallel Multi-Processor Initialization Process Disclosure Number: IPCOM000036879D
Original Publication Date: 1989-Nov-01
Included in the Prior Art Database: 2005-Jan-29

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Pfeiffer, RT [+details]


Disclosed is a concept which modifies the Initial Microcode Load sequence from a series of sequential steps into a highly parallel process. This concept implements a computer system of multiple processor units where each processor unit maintains both its program load and run-time parameters in a special non-volatile memory. The non-volatile memory allows each processor unit to function as an independent unit during system initialization.