Browse Prior Art Database

Decoder-Initiated Prefetching for LONG OP Instructions

IP.com Disclosure Number: IPCOM000036883D
Original Publication Date: 1989-Nov-01
Included in the Prior Art Database: 2005-Jan-29

Publishing Venue

IBM

Related People

Authors:
Emma, PG Knight, JW Pomerene, JH Puzak, TR Rechtschaffen, RN [+details]

Abstract

Several instructions in the 370 architecture have the capability to fetch from, or store into, multiple cache lines during a single execution of an instruction. For example: The STM instruction can store up to 64 bytes of information if all 16 registers are specified in the instruction's format. The MVC instruction can fetch and store up to 256 bytes of contiguous information. The MVCL instruction commonly is used to fetch and store several thousand bytes of contiguous information.