BUS Fault Identification Algorithm
Original Publication Date: 1989-Nov-01
Included in the Prior Art Database: 2005-Jan-29
This algorithm uses hardware status collected at the time of a system bus failure to identify the cause of intermittent and stuck failures, independent of the number and location of I/O bus units (IOBU) on 1 to 8 boards. The algorithm is the basis for subsequent actions to provide uninterrupted bus operations by either recovering the failing operation and recording statistics for error thresholding or disabling the failing IOBU pending its repair. The problem of identifying the cause of bus operation failures is complicated by the wide range of configurations. The communicating bus units may be on the same board as the processor, separated from the processor by multiple boards, or may be separated from each other by multiple boards.