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Address Adder With 100% Checking and Fast Parity Predict Disclosure Number: IPCOM000036911D
Original Publication Date: 1989-Nov-01
Included in the Prior Art Database: 2005-Jan-29

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Weinberger, A [+details]


The figure shows the major elements of the address adder designed for 100% checking and a fast parity predict path. Complete checking means that every single stuck fault (stuck-at-0 and stuck-at-1) of an input and an output of a gate is detected. Each of two outputs of a gate may be in error independently.