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This article describes a terminal count timing scheme for a personal computer system which eliminates direct memory access (DMA) synchronization errors in buffered floppy disk controller applications.
English (United States)
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Terminal Count Timing Scheme for a Personal Computer System
This article describes a terminal count timing scheme for a personal
computer system which eliminates direct memory access (DMA) synchronization
errors in buffered floppy disk controller applications.
One of the problems encountered when attaching an external first- in/first-out
(FIFO) data buffer between standard floppy disk controller (FDC) chips and a
host system is that the host DMA controller will operate asynchronously with the
FDC any time more than one byte remains in the buffer. During a diskette write
operation, for example, the external data buffer may be full after the DMA
controller transfers its last byte and has issued terminal count (TC), but the FDC
must empty the buffer before it is prepared to receive the TC signal indicating
that the transfer is complete. If TC is received before the external data buffer has
been emptied, the data remaining in the buffer will not be written to the diskette
and data loss will occur.
Similarly, during diskette read operations, if more than one byte remains in
the external data buffer after the FDC has read the last byte of the sector, the
DMA controller will not issue TC until it has emptied the buffer, causing a delayed
TC to be received by the diskette controller. In this case, the FDC will attempt to
read the next sector and an error will be reported because the DMA controller is
not prepared to transfer this additional data.
In the technique disclosed herein, a special transfer counter is added to the
external data buffer, as depicted in the drawing. The multiplexer is used to
intercept the DMA TC signal so that it is not passed directly to the floppy disk
controller. Instead, a separate floppy disk controller TC signal (FDCTC) is...