Four Device Complementary Metal Oxide Silicon Quasi Static Random Access Memory Cell
Original Publication Date: 1989-Nov-01
Included in the Prior Art Database: 2005-Jan-29
This four-device circuit has operational characteristics of a six- device static random-access memory (SRAM) cell when p-type device leakage exceeds subthreshold device current of its n-type devices. A refresh cycle or a word line driver circuit which does not pull the word line all the way up to supply voltage (Vdd) is required if p-type leakage is not excessive.