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Circuitry has been proposed which permits an accurate, fixed delay time to be introduced in a signal path in semiconductor devices. The proposal uses an extremely tight tolerance of +8% in the delay block.
English (United States)
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Circuitry has been proposed which permits an accurate, fixed delay time to
be introduced in a signal path in semiconductor devices. The proposal uses an
extremely tight tolerance of +8% in the delay block.
The proposed delay circuit has been designed using chip technology in
combination with two external timing control components, one resistor (R) and
one capacitor (C). These fix the nominal delay time (Td) in nanoseconds
according to: Td = 0.498(RC) +4.29
In this proposal R = 450 L, a 1% tolerance, and C = 200 pF, a 3% tolerance,
for a Td = 49.1 nS. The delay pulse is timed from a falling transition on the input
to a falling transition on the output.
The circuitry as proposed has three basic sections: an input driver to control
the exponential rise on the external components; a high speed emitter-coupled
switch with hysteresis; and a level shifter. The bulk of the delay time is caused
by the rising exponential. The circuit is accurate to within 8% of overall nominal
conditions, not including noise.
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