Instruction Cache Bypass During Cache Reload Operation
Original Publication Date: 1989-Nov-01
Included in the Prior Art Database: 2005-Jan-29
The time between the request for a cache line and the subsequent return of that cache line from memory is long enough in most cases to deplete the instructions available for dispatch to the execution units of a computer system. A further delay can be incurred if the instructions must be written to the cache and then fetched from the cache once the line has been completely transferred from main memory. A method will be described which tries to minimize the effects of this problem by bypassing instructions directly to the instruction unit as they return from memory.