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IMPROVED CMOS DEVICE STRUCTURE AND FABRICATION PROCESS USING SELECTIVE DEPOSITION OF TiSi2

IP.com Disclosure Number: IPCOM000036996D
Original Publication Date: 1989-Nov-01
Included in the Prior Art Database: 2005-Jan-29

Publishing Venue

IBM

Related People

Authors:
Harper, JME Krusin-Elbaum, L Thomas, O Joshi, R [+details]

Abstract

The current technique for sub-micron CMOS fabrication (0.25 mm will be used as a reference) uses the deposition of 150 angstroms Ti on S/D regions, followed by a multi-step reaction/etch/anneal process to form self-aligned TiSi2 on S/D, about 300 angstroms thick. This process has limited success in smaller devices because of uneven formation of the silicide, instability at high temperature, consumption of doped Si leading to high contact resistance, and bridging to the gate. The high annealing temperature also degrades the dopant profile.