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Dynamic Cache Line Delete Disclosure Number: IPCOM000037006D
Original Publication Date: 1989-Nov-01
Included in the Prior Art Database: 2005-Jan-29

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Related People

O'Leary, BJ Sutton, AJ [+details]


A Processor system Cache design has a Directory for determining residency of data within the Cache. The Directory is organized as set associative, with each address entry reflecting a Cache 'line' (typically, 16 doublewords). Along with the Directory address, there exists a deletion bit which, when set, removes usage of the corresponding line of Cache data.