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Simple and High Performance Support for IEEE Floating Point Exceptions

IP.com Disclosure Number: IPCOM000037033D
Original Publication Date: 1989-Nov-01
Included in the Prior Art Database: 2005-Jan-29

Publishing Venue

IBM

Related People

Authors:
Groves, RD [+details]

Abstract

High-speed support for IEEE floating point exceptions in a highly overlapped machine require careful trade-offs between software and hardware. Because the IEEE standard trap mode requires precise interrupts, the synchronization and/or hardware complexity implied either significantly increases design complexity and/or adversely affects system floating point performance. As an alternative for this class of machines, a set of retrospective diagnostics and floating point modes to provide the most useful aspects of the IEEE trap modes has been proposed. While many other machines are implementing this alternative, they all still support some form of high speed precise interrupt. What is described here is a combination of hardware and software without requiring the high-speed precise interrupt.