Package Level Programmable Chip Architecture
Original Publication Date: 1989-Nov-01
Included in the Prior Art Database: 2005-Jan-29
Steering circuits are included on dynamic random-access memory (DRAM) chips which may be programmed by appropriate connection to one or more program pads at the time of packaging to select a desired architecture. Thus, chips with identical construction may be configured to meet different architectural requirements late in the manufacturing cycle and fewer part numbers exist in the manufacturing line.