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Parallel Architecture for High Speed Bit Stuffing and Byte Alignment Disclosure Number: IPCOM000037039D
Original Publication Date: 1989-Nov-01
Included in the Prior Art Database: 2005-Jan-29

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Ancheta, T Birman, A Guerin, R Chang, PC [+details]


This article describes a high speed parallel architecture for performing bit-stuffing (0-bit insertion and deletion) and byte-alignment functions used in packet communications. These functions are described by means of finite-state representations which result in a modular design.