SET/RESET System With Slow SET and Fast RESET
Original Publication Date: 1989-Nov-01
Included in the Prior Art Database: 2005-Jan-29
Disclosed is a circuit that performs a SET/RESET function with priority to RESET, SET being generated by a slow process (typically, a DTE application) and RESET being generated by a fast process (typically, a microprocessor application). The circuit has been sucessfully implemented on a CMOS gate-array showing a significant size improvement over existing equivalent designs, with no AC performance impact.