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VLSI Testing Method for Individual Chips Disclosure Number: IPCOM000037117D
Original Publication Date: 1989-Nov-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 4 page(s) / 93K

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Le, TN: AUTHOR [+2]


Disclosed is a method to individually test and assure functionality of an individual VLSI chip of a chip set in which chips interact with each other to perform complex functions.

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VLSI Testing Method for Individual Chips

Disclosed is a method to individually test and assure functionality of an individual VLSI chip of a chip set in which chips interact with each other to perform complex functions.

Very complex and large-scale integrated chips, employing thousands of circuits, are usually simulated to verify logic design prior to fabrication. Software simulation is usually performed by running test case programs on a logic design model and comparing the results with predicted expectations. Software simulation allows one to record internal states of circuits for every simulation cycle. Once any individual chip of a set is manufactured, it is an exceedingly important task to verify the hardware functions according to the design goal. If all chips of a set are not available simultaneously, this task requires special methods to verify functionality of a subset, and even if the entire chip set was available, many times it is necessary to localize a problem. The method described herein is an approach to achieve this goal for an LSSD-compatible design. It addresses a way to set an individual chip (of a processor chip set) to a known state and feed its inputs with predetermined patterns, stimulate and predict the output patterns.

LSSD chip design lends itself to a convenient setting of an internal state by scanning a known pattern in its scan string. This proce- dure takes advantage of this feature. Software simulation allows one to obtain a pattern corresponding to the internal states of storage elements. Each bit of this scan string data pattern corresponds to an input of an internal latch. The pattern is scanned into the chip to set an initial state of the chip at the start of that functional behavior. The chip is then set in a "run" mode to run at system speed for 'n' cycles, following which the outputs are scanned and compared to an expected pattern. Any mismatch leads one to identify the problem circuit.

The designer provides a list of facility names or net names corresponding to all data bits of a complete scan string. Using this list, simulation of any application test case program generates a data pattern which represents internal states of the entire chip at any 'm'th cycle after the start. Fig. 1 shows a sample of such a list. DCT0ARR_E_OUT_$ DM13MEM_MUX_C$ SS0_SEAR_DAT_IN$ DCT0ARR_O_OUT_$ SRB_BUS1_EN$ ZIO_BUS1_0$ DCT0PTS_$ SRB_BUS_IN_USE_$ ZIO_BUS1_PTY_0$ DCT0R_B1B2_DEC_$ SRB_LDST_ON_BUS$ ZIO_BUS1_1$ DIC3LD_BUFFER$ SRB_BUS1_ENDSEQ_$ ZI)_BUS1_PTY_1$

Fig. 1 Sample of a list of net names, Fig. 2 shows a typical sample of a scan file obtained via software simulation. ******PLEASE SEE ORIGINAL FOR FIGURE 2 ****** Fig. 2 Sample of a scan file

LSSD-compatible chip will require an additional simple test hard- ware to serially scan in the initialization data pattern. Once the scan string is fed, the chip internal state initialization is complete. A similar net list for all primary inputs will facilitate the genera...