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Optimized Incremental Delay Generator

IP.com Disclosure Number: IPCOM000037125D
Original Publication Date: 1989-Nov-01
Included in the Prior Art Database: 2005-Jan-29

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Related People

Erdelyi, CK Marshall, MG Mathews, JW [+details]


Two-input, single-output circuit blocks, e.g., OR circuits, of nearly identical construction are assembled in an array, resulting in an output having been delayed an amount of time dependent on the input addressed. Thus different delays in predictable increments are available from the data paths constructed. Such circuit capability is utilized when writing data on a storage disk, for instance. (Image Omitted)