Bias Circuit for Active Pull-Down ECL Output Stage
Original Publication Date: 1989-Nov-01
Included in the Prior Art Database: 2005-Jan-29
Disclosed is a new circuit implementation which achieves the desired standby current in the output stage of an active pull-down (APD) ECL gate without the need of the large emitter resistor and speed-up capacitor while maintaining the same speed advantage. The active area required for the gate is substantially reduced and the current sink capability is no longer limited by the emitter speed-up capacitor. In addition, the emitter of the pull-down transistor can now be tied to VTinstead of VEE as shown in the figure, thereby further reducing the DC power dissipation of the gate. The DC bias network for the pull-down device is very simple, controllable and dissipates very little power. This implementation is compatible with ECL gate array application as no new component is required.