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MINIMIZING POWER IN HIGH PERFORMANCE PLAs

IP.com Disclosure Number: IPCOM000037165D
Original Publication Date: 1989-Nov-01
Included in the Prior Art Database: 2005-Jan-29

Publishing Venue

IBM

Related People

Authors:
Ditlow, GS Busch, R [+details]

Abstract

When designing high performance PLAs, minimizing power is a critical design issue. In this article, an algorithm is presented which personalizes the p-device pull-ups in the AND-array to significantly reduce DC power.