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A double polysilicon buried contact CMOS process is described which avoids concerns associated with conventional buried contact processing on ultra thin gate dielectrics.
English (United States)
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Double Poly Buried Contact Process
A double polysilicon buried contact CMOS process is described which
avoids concerns associated with conventional buried contact processing on ultra
thin gate dielectrics.
A current CMOS buried contact process utilizes a photoresist mask to open
areas in the gate oxide. After stripping the resist, approximately 235 angstroms of
polysilicon is deposited on the wafer. Concerns over the adverse effects resulting
from cleaning steps on the gate oxide integrity, and polysilicon bumps that
nucleate from the buried contact process residuals, indicate that this process is
not desirable for future programs. Future generation gate oxides will be in the
135 angstrom range and bumps will be intolerable (cannot overetch as much on
the thin gate oxide to remove the bumps). A new double poly buried contact
process eliminates the defect concerns described.
Referring to the figure, a gate oxide is first grown on the wafer, i.e., 135
angstroms. Next a 1,000-angstrom film of intrinsic polysilicon is deposited on top
of the gate oxide. The buried contact photo process follows, and the polysilicon is
then etched using conventional techniques. The gate oxide is removed in a 10:1
BHF. After the resist is stripped, a low energy silicon implant is performed to
damage the surface in order to prevent the formation of a thin oxide. A final layer
of polysilicon (approximately 3,300 angstroms) is then deposited.
Another technique for avoiding the formation of...