NA Generation for Fast Memory Access in a 386-Based System
Original Publication Date: 1989-Nov-01
Included in the Prior Art Database: 2005-Jan-29
Disclosed is a method to attain high performance memory access speeds by clever utilization of the pipeline feature of the 80386SX CPU (running at 16 Mhz) such that external hardware is minimized. In addition to low cost as a design objective, a performance target of 0 wait states (with 100 ns memory) was set for CPU accesses to planar memory. In order to achieve this goal, the bus controller and memory controller utilized the full capability of the 80386SX address pipelining feature.