Parallel Processing of Addresses for Fast Cache Access
Original Publication Date: 1989-Nov-01
Included in the Prior Art Database: 2005-Jan-29
To improve computer cycle time, small adder circuits are used to permit the start of small random-access memory (RAM) files ahead of generation of a complete effective address in a large, slower adder circuit. Multiplexers and compare circuits are added to check that segment file addresses generated early by the small adders match the addresses generated later by the large adder circuit and to make corrections in the event of a mismatch.