Soft-Error Free Differential ECL Latch
Original Publication Date: 1989-Dec-01
Included in the Prior Art Database: 2005-Jan-29
A generic Differential ECL latch is shown in Fig. 1. The data is fed into the latch through transistors 1 and 2, and transistors 3, 4, 5 and 6 form a feed-back loop that latches the data. The data is stored at node A (or B). When the data D=1, node B is high and node A is low, and the data is latched when CLK=0.