Transmission Delay Cancellation Mechanism on Very High Speed Bidirectional Buses
Original Publication Date: 1989-Dec-01
Included in the Prior Art Database: 2005-Jan-29
On a high speed bus (around 30 ns cycle) where delay transmission on a medium is significant versus cycle time, the best way to ensure correct data latching at the receiving end is to send a sampling clock along with the data bus. However, this solution can be impractical in a multichip or multicard situation. Classical asynchronous techniques introduce extra heavy hardware and logic layers. The present disclosure offers a simple solution able to self-adapt to different hardware implementations. Consider Fig. 1, where one Central Switch Node (CSN) connects 1 to N satellites.