Cache Miss Leading Edge Processing
Original Publication Date: 1989-Dec-01
Included in the Prior Art Database: 2005-Jan-29
Improvements in the operation of a memory hierarchy are derived by utilizing the "leading edge" of a cache miss to anticipate additional hierarchical requirements. Current high end processors are limited in several ways by the occurrence of an operand cache miss. In some processors the architectural requirements that operands must be accessed in sequence precludes accessing beyond the point where a cache miss has been recognized. Even if this limitation is relaxed, the accessing of the cache is limited by the available queueing facilities within the processor. In the following neither of these limitations apply as the results of the cache accessing are utilized for the sole purpose of instructing the memory hierarchy.