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Modular Technique for Constructing Control Logic of a Pipelined Processor

IP.com Disclosure Number: IPCOM000037369D
Original Publication Date: 1989-Dec-01
Included in the Prior Art Database: 2005-Jan-29

Publishing Venue

IBM

Related People

Authors:
Matick, RE [+details]

Abstract

A technique is described whereby a set of modular building blocks and macros are interconnected by means of a uniform, standard interface to be used to design control logic of any pipelined processor. The blocks are designed so that they can be implemented in software as a modular timer, so as to provide an evaluation tool of relative instruction execution performance of any given pipeline.