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A fast parity tree is shown which can improve a parity generator delay performance by about 80% while maintaining the same macro size over a previous design. (Image Omitted)
English (United States)
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Fast Parity Tree
A fast parity tree is shown which can improve a parity generator delay
performance by about 80% while maintaining the same macro size over a
A parity generator and checker are required in a microprocessor to either
create the parity bit to be stored or check the integrity of the data read. When the
parity generator is connected in series in one of the critical paths of a processor,
the delay of the circuit is reflected directly on processor performance. The
existing parity generator is designed as a chain of Exclusive-OR (XOR) circuits.
The XOR is designed as a 2-way NOR followed by 2 + 1 AND-OR-Invert circuit.
The total number of delay stages is 7 for a total delay of 5.6 ns. A new parity
generator, where the XOR and XNOR are generated at each level of the tree, is
utilized to reduce the total number of logic delays. The new circuit results in an
80% improvement in delay with no impact on macro density.
The new parity generator uses an XOR circuit that requires true and
complement inputs. Figs. 1 and 2 show the different implementations of the XOR
and XNOR circuit that can be utilized for the parity tree. Both implementations
have the same circuit configuration for XOR and XNOR, only some input
connections are switched. Fig. 3 shows the logic diagram of the parity generator
with the total number of logic delays reduced to 5. In this parity tree, the XOR
and XNOR functions are generated in parallel...