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Bypass Latch Control of Long Shift Register Strings

IP.com Disclosure Number: IPCOM000037387D
Original Publication Date: 1989-Dec-01
Included in the Prior Art Database: 2005-Jan-29

Publishing Venue

IBM

Related People

Authors:
McAnney, WH [+details]

Abstract

Two methods are shown for reducing the time required to shift data into or out of portions of long serial paths in level-sensitive scan design (LSSD) structures. The structure consists of large numbers of shift register latches (SRLs) on each of n logic chips mounted on a wiring substrate or module. The scan-out port of one chip drives the scan-in port of the next, and all SRLs are chained together into one long shift register string. With this structure, some additional control over the string is desirable to reduce the time required to shift data to or from an individual chip or groups of chips. This control can be obtained with a bypass SRL that provides, on demand, a single-bit serial connection through a chip. Test access time to a single chip is reduced by planing the other n-l chips in bypass mode.