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Low-Cost Signature Analyzer and an Application Disclosure Number: IPCOM000037388D
Original Publication Date: 1989-Dec-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 8 page(s) / 198K

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Bardell, PH: AUTHOR [+2]


Fig. 1 shows a NAND implementation of a polarity hold latch and its symbol as used in this article.

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Page 1 of 8

Low-Cost Signature Analyzer and an Application

Fig. 1 shows a NAND implementation of a polarity hold latch and its symbol as used in this article.

Six of these polarity hold latches are shown connected into a 6-stage multiple-input signature analyzer in Fig. 2. The data bit streams entering the analyzer are represented by Ai, Bi, Ci, Di, Ei, and Fi. The latches of Fig. 2 are clocked by either Clock R or Clock Q, a pair of non-overlapping clocks as shown here.

(Image Omitted)

Notice the alternate use of Clock R and Clock Q in the latches of Fig. 2. This alternation is continued whatever the length of the signature analyzer. Operation

The latches of Fig. 2 are initialized to 0. The first bits of the input sequence (A1, B1, C1, D1, E1, and F1) are applied during the first R/Q Clock cycle, after which the latch contents are: Stage 1: A1

Stage 2: A1+B1

Stage 3: C1

Stage 4: C1+D1

Stage 5: E1

Stage 6: E1+F1

(Image Omitted)

where + means addition modulo-2.

For the next two R/Q cycles the contents are

Second R/Q Cycle Third R/Q Cycle

Stage 1: A2+C1+D1+E1+F1 A1+A3+B1+C1+C2+D1+D2+E2+F2 Stage 2: A2+B2+C1+D1+E1+F1 A1+A3+B1+B3+C1+C2+D1+D2+E2+F2 Stage 3: A1+B1+C2 A2+B2+C1+C3+D1+E1+F1 Stage 4: A1+B1+C2+D2 A2+B2+C1+C3+D1+D3+E1+F1 Stage 5: C1+D1+E2 A1+B1+C2+D2+E3 Stage 6: C1+D1+E2+F2 A1+B1+C2+D2+E3+F3 and so forth.

Note that the end signature depends on all bits that have entered the analyzer. Extensive computer simulation with the analyzer of Fig. 2 shows that this is true in each case examined.

Concerning its aliasing characteristics (aliasing is the mapping, through the signature analyzer, of an erroneous data stream into the correct signature): Simulation results show that the aliasing probability of this signature analyzer is about 2-n/2 . Construction of the Feedback

(Image Omitted)


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Suppose that inputs Bi, Ci, Di, Ei, and Fi of Fig. 2 are always 0 (so we can remove the XOR at those inputs). Also suppose that Clock R is renamed Clock A, and similarly Clock Q is renamed Clock B. Making these changes, Fig. 2 is redrawn as Fig. 3. Now mentally reconstruct latches 1 and 2 into an LSSD shift register latch.

Do the same with latches 3 and 4, and with 5 and 6. We see then that Fig. 3 is a 3-stage linear feedback signature analyzer implementing the primitive polynomial 1 + x + x3 .

(Image Omitted)

So construction of the feedback is obvious. Choose a primitive polynomial of degree n/2. Build the linear feedback analyzer implementing this feedback as in Fig. 3. Finally, make the transformation as in Fig. 3 to Fig. 2.

An Application: The source of the data being compressed in Fig. 2 was not specified. We are free to assume it to be the output of an L1 latch. Similarly, the latches of the signature analyzer can be L2 latches with the analyzer inputs being additional latch data ports. The structure is shown in Fig. 4 (where the scan path and shifting clocks are omitted for clarity). Note that the added L2 data ports are connected alternately...