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Memory access time is significantly reduced in multi-processor computing systems by providing a memory-level pre-stage cache to service predictable memory accesses.
English (United States)
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Memory Cache for Prefetching
Memory access time is significantly reduced in multi-processor computing
systems by providing a memory-level pre-stage cache to service predictable
Although each processor in a multiple processor system may have its own
cache, another cache is provided at the memory level, designated pre-stage
cache. The pre-stage cache has its own directory, is structured as set-
associative and uses a replacement policy, such as least recently used or first in-
first out. Upon a cache miss, for example, on line L from a processor, another
line L' is staged to the pre-stage cache if a subsequent cache miss to L' is
anticipated via some mechanism. Memory access that hits to the pre-stage
cache will be fetched from there.
Line staging to the pre-stage cache depends on the particular
implementations and the following are examples:
a. Pre-stage the sequential next line upon a miss unless other
information is available to save the pre-staging;
b. Pre-stage a block of lines upon a miss to a private
processor cache. A block may cover the other three lines in a
c. Steer pre-staging by the processors indicating
instruction-fetch or other access type;
d. Pre-staging decisions may be assisted with historical
As variations, the pre-stage cache can be read-only used for fetch misses, be
provided for each system module, or have a granularity different from line sizes
of other caches. Pre- staging of data into a pre-st...