Parity Generation without Increasing Machine Cycle Time
Original Publication Date: 1989-Mar-01
Included in the Prior Art Database: 2005-Jan-29
The logic circuit described checks for parity errors in registers that could arise during a single machine cycle or during a longer period for which a register inhibit is active without adding delay time. This method is especially useful for combinational logic, where parity propagation is impractical and parity generation is often added just before logic output feeds into registers, thus increasing machine cycle time.