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A circuit is shown which decreases the standby power of a receiver and also provides a clipping function to avoid high electric field stresses in the chip.
English (United States)
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Low Power Receiver for Interfacing a 5 Volt Input Signal with a 3.4 Volt
A circuit is shown which decreases the standby power of a receiver and also
provides a clipping function to avoid high electric field stresses in the chip.
The receiver interface circuit shown in the figure is designed to work in a chip
that has a power supply whose value is significantly lower than the input signal to
the receiver. The interface circuit provides flexibility when setting the switch
points of the receiver. Also, the standby power is decreased when used with
other CMOS circuits with a 3.4 or 5.0 volt power supply.
The circuit shown has the ability to accept inputs which exceed 3.4 volts
while remaining in a low power mode. T1 is inserted in the circuit to monitor the
actual input voltage swings. If 5 volts is applied to the input, T4 passes slightly
more than 2 volts, while T1 sees the entire voltage. T1 turns off, and T2, which is
initially on, turns off too as it leaks down the connecting node A between T1 and
T2. Node A drops to about 2.6 volts and then floats at that level. As a result, T3 is
the only device left on and the DC path to ground is shut off. In the other
direction, the DC path will only be turned off completely when the input drops
below a Vt above ground potential.