Method to Achieve Equal Capacitance on a Group of Nets During Circuit Layout And Placement
Original Publication Date: 1989-Mar-01
Included in the Prior Art Database: 2005-Jan-29
An enhancement added to a circuit placement algorithm allows constraints requiring certain groups of circuit networks to have nearly equal capacitance. The enhanced algorithm reduces variation in time of arrival of clock pulses (clock skew) to circuits being placed in various locations in very large scale integrated (VLSI) circuit chips. Thus, chip cycle time and system performance is improved.