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A CMOS semiconductor structure is shown which utilizes existing technology features to implement a polysilicon-to-N+ or Pdiffusion contact in a minimal area.
English (United States)
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Mimimum Area Floating Gate Tie-Down Structure
A CMOS semiconductor structure is shown which utilizes existing technology
features to implement a polysilicon-to-N+ or Pdiffusion contact in a minimal area.
A process ground rule requiring all polysilicon lines that form gates be
contacted to a diffusion after the first level metal (M1) can be satisfied through
the utilization of a structure shown in the figure. A polysilicon (PC) line partially
intersecting an area above a diffusion is shown in the top view. A narrow
rectangular contact area (CA) opening extends from over the PC line to the
diffusion area below. A cross-section shows tungsten (W) fill metal in the contact
area providing a tie-down structure from the polysilicon line (floating gate) to the
The new structure provides the following advantages:
1. No additional process steps are required.
2. A smaller contact area is required than separate M1 contacts
to polysilicon and diffusion.
3. No metal line is required above the contact, minimizing the
impact to adjacent M1 wiring.