Browse Prior Art Database

Mimimum Area Floating Gate Tie-Down Structure

IP.com Disclosure Number: IPCOM000037796D
Original Publication Date: 1989-Jul-01
Included in the Prior Art Database: 2005-Jan-30

Publishing Venue

IBM

Related People

Authors:
Craig, WJ Cronin, JE [+details]

Abstract

A CMOS semiconductor structure is shown which utilizes existing technology features to implement a polysilicon-to-N+ or Pdiffusion contact in a minimal area.