Zero Threshold Voltage Device
Original Publication Date: 1989-Jul-01
Included in the Prior Art Database: 2005-Jan-30
By making channel width smaller in array devices than in support circuit devices, enhancement mode transistors having oxide filled trench isolation are made to have threshold voltage (VT) near zero for array devices while retaining a normal, higher VT in support circuit transistors. This technique avoids processing additions which are usually required to create transistors of different VT values on the same chip or wafer.