Alignment Aid for Stud Up Technology
Original Publication Date: 1989-Jul-01
Included in the Prior Art Database: 2005-Jan-30
A semiconductor alignment aid may be formed in a planar surface by placing a vertical metallurgical "stud up" structure generated in the normal process sequence in a large (non-functional) area. The resulting "artificial" valley created on the chip represents the deepest valley on the chip. In so doing, the etching of the studs and insulator result in exposing the stud mask in this area and the stud conductor everywhere else. By wet etching the stud mask preferential from the field and stud metal areas, a topographical alignment aid is created first order to the stud level.