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When a power supply voltage is applied, flip flop (F/F) type circuits in differential cascode current switch logic can have undefined output logic levels.
English (United States)
This text was extracted from a PDF file.
This is the abbreviated version, containing approximately
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Output Logic Level Control of Flip-Flop Integrated Circuits
When a power supply voltage is applied, flip flop (F/F) type circuits in
differential cascode current switch logic can have undefined output logic levels.
To condition the output voltage of F/F type circuits to both logic levels for
testing, a novel method is provided for setting an output in the down level, while
using conventional F/F circuitry. An F/F circuit conventionally interconnects two
data latch circuits. The FIGURE depicts a data latch connected as the output half
of a typical F/F circuit. Outputs 01 and 01N drive additional logic.
Heretofore, transistor Q1 set output 01 in the down level for testing by
applying a voltage on the base of Q1 (TESTP) higher than the up level clock
In the present technique, however, the voltage on TESTP is set about 0.9
volts higher than supply +V. Voltage 0.9 is a transistor VBE plus 100 mV. This
forward biases the base-emitter and base-collector junctions of transistor Q1.
Current I1 flows from the voltage supply driving TESTP, through the base-emitter
junction of Q1 and into the current source. Current also flows from the TESTP
supply, through the base-collector junction of Q1, through resistor R1 and into
supply +V. The current through resistor R1 sets the voltage on output 01 to
about 100 mV above supply +V. No current flows through resistor R2, so the
voltage on output 01N is equal to +V. These conditions set output 01N in the
down level or 100 mV b...