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Design Methodology for Test Time Reduction in Dynamic Random-Access Memory Disclosure Number: IPCOM000037948D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-31

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Hovis, WP DiLorenzo, J Nickel, DJ Yankowski, JA Kalter, HL Drake, CE Lewis, SC Fifield, JA [+details]


Dynamic random-access memory (DRAM) test time is reduced by using an internal high-speed static random-access memory (SRAM) as an interface. SRAM positions normally addressed individually can be examined collectively by using an exclusive OR (XOR) circuit.