Design Methodology for Test Time Reduction in Dynamic Random-Access Memory
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-31
Dynamic random-access memory (DRAM) test time is reduced by using an internal high-speed static random-access memory (SRAM) as an interface. SRAM positions normally addressed individually can be examined collectively by using an exclusive OR (XOR) circuit.