Programmable Pseudo Random Extended Forward Reverse Counter
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-31
In order to generate a series of bits whose length, sequence and direction of progression are controlled by a user, a logic controlled LSSD counter is herein disclosed. The counter is a programmable pseudo random extended forward reverse counter (Programmable-PREFR) designed to test a combination of parts. It can also be a self-test device for diverse logic functions on the same assembly. Standard LSSD design is utilized for the counter.